1. Field of Invention
This invention relates to semiconductor integrated circuit testing and in particular burn-in testing of semiconductor memory devices.
2. Description of Related Art
In recent improvements in the CMOS process, the junction and gate-oxide breakdown has become smaller as the semiconductor geometry has become smaller. Because the junction and gate-oxide breakdown voltage is smaller, the available maximum stress voltage without concern for wear-out is also smaller.
A substrate back bias voltage is used to reduce sub-threshold current and junction capacitance, to improve device isolation, to enhance latch-up immunity, and to protect circuits from voltage undershoot of the input signal. This back bias further constrains the maximum stress voltage in burn-in which lengthens the required time in burn-in testing in order to guarantee short term and long term failure rates.
In U.S. Pat. No. 5,657,282 (Lee) is discussed a semiconductor integrated circuit having a stress circuit and a stress voltage to ensure the reliability of the integrated circuit. During test, multiple stress voltages are applied to various parts of the integrated circuit to determine weak and defective circuitry. In U.S. Pat. No. 5,467,356 (Choi) a burn-in enable circuit and a burn-in test method are disclosed. A higher than normal voltage is applied to a semiconductor memory chip. This voltage is detected by a burn-in test enable circuit and causes reset operations of word lines to be disabled, allowing the stress voltage to be applied to all access transistors simultaneously, and reducing burn-in time. In U.S. Pat. No. 5,349,559 (Park et al.) a circuit is described that generates an internal voltage for a semiconductor memory during normal operations and allows an external voltage to be used during burn-in operations. In U.S. Pat. No. 5,119,337 (Shimizu et al.) the substrate voltage of a semiconductor memory device is controlled to be lowered by means of a burn-in mode detection circuit. This allows the word line drive signal to be higher than normal to apply a stress voltage on the memory cells.
The purpose of burn-in for semiconductor memory devices is to guarantee both short term and long term failure rates to meet user specifications and requirements. These requirements establishes a need to screen out process intrinsic defects such as particles, residue and latent defects and to detect process reliability items such as metal line integrity, contact electromigration, and stress migration. To carry out a sufficient burn-in test, there is a relationship between the level of stress and the time in a burn-in test. Newer devices have thinner oxides and smaller geometry resulting in lower breakdown voltages. It thus becomes important with new devices to find a means to provide a sufficient level stress in order to contain the burn-in test time.